We have an exciting opportunity for a Design Verification Engineer in Krakow, Poland

Job Title: Design Verification Engineer
Location: Krakow, Poland (On-site)

I’m currently hiring for a Design Verification Engineer role in Krakow, and I think it could be a strong match based on your background.

This is a company working at the heart of semiconductor innovation, helping teams design and integrate complex SoCs used across smartphones, EVs, smart devices, drones, satellites, and cloud datacentres, essentially the technology powering modern computing everywhere.

Why this role is exciting:

• Work on advanced SoC assembly and register generation flows
• Influence verification, tooling, and methodology in a highly technical EDA environment
• Contribute to technologies used across automotive, consumer electronics, AI, and high-performance computing

What you’ll do:

• Develop and execute simulation-based verification for a Register Bank compiler (Cadence, Synopsys, Siemens tools)
• Build Python-based validation flows (IP-XACT, C headers, documentation)
• Enhance CI pipelines, automation, and verification metrics
• Collaborate with developers on testing strategies and participate in code reviews

What they’re looking for:

• 7+ years RTL/DV experience
• Strong SystemVerilog + UVM expertise
• Solid Python scripting skills
• Understanding of VHDL/Verilog
• Experience with IP-XACT / C-HAL / equivalence checking (nice to have)
• Curious, autonomous, and quality-driven mindset

Why consider it:

• Permanent role with a competitive, negotiable salary
• Strong technical ownership and impact on methodology
• Collaborative, engineering-driven environment